The present application is generally directed to a method and circuit for detecting faults in or degradation of a digital clock pulse signal used for synchronization in digital systems. More particularly, the present application is directed to a method and circuit for detecting faults or degradation in a clock pulse signal utilized in a digital communications network, particularly for synchronization of the network.
Over the last twenty years, digital processing of information has become increasingly important. Digital telecommunication and data communication networks are utilized in virtually every aspect of modern life. The use of digital clock pulse signals is common in all forms of digital information processing. Digital telecommunication or data communication networks are systems that often use clock signals, for network synchronization, which synchronization may be necessary to avoid loss of information transported between different nodes of the network or communication system.
Because of the importance of such clock pulse signals, such signals are often transmitted redundantly. Also, because of the importance of such clock pulse signals, it is desirable to supervise the generated clock pulse signal, setting an alarm if the clock pulse signal degrades or fails. Such an alarm can, in turn, be used to control other network functionality, for example, to switch in a standby clock pulse signal generator or to remove the faulty clock pulse signal using majority vote logic.
The supervision or monitoring of clock pulse signals has been performed in the past by means of a detector generally known as a loss of signal (xe2x80x9cLOSxe2x80x9d) detector. Such LOS detectors will monitor the amplitude of the pulses produced by the digital clock pulse signal and will generate an alarm when the magnitude of the clock pulses decay below a threshold. Such LOS detectors are often slow to react to a gradual decay of the digital clock pulse signal, and thus may not detect faults or degradation sufficiently quickly. Further, such loss of signal detectors are not capable of detecting spurious pulses in the digital clock pulse signal, which spurious pulses may be caused, for example, by the jiggling of a connection to a cable used to transmit the digital clock pulse signal.
Another known method of monitoring or supervising a digital clock pulse signal is to sample the supervised clock with a detector having a sampling rate substantially higher than that of the supervised clock. While this can be effective when the clock frequency of the digital clock pulse signal is relatively low, this is not practical when the frequency of the supervised clock is high. Additionally, this type of detector can confuse a bunst of noise pulses as a correct signal.
Another possible method of detecting or monitoring clock pulse degradation is to detect whether a logical low-to-high transition (leading edge) or high-to-low transition (trailing edge) is received within a predetermined measurement interval. However, such a method may not readily detect noise pulses within the digital clock pulse signal. Effectively, this known method of monitoring takes snapshots of the monitored digital clock pulse signal, sampling it at periodic times. Because the signal is only periodically sampled, this known method may miss glitches in the monitored clock pulse signal of less than a clock period and length period.
The known detectors generally work acceptably when the clock pulse signal is started or discontinued in a controlled way, for example when controlled by an electronic gate resistant to pulse bounce. However, there are a number of fault situations that are not detected by such prior art detectors. For example, a cable transmitting the digital clock pulse signal may be removed, or the power to the clock pulse generator may be switched off, thereby causing unexpected digital clock pulse signal behavior. For example, when a clock cable with an active clock pulse signal is disconnected while transmitting the digital clock pulse signal, noise may be produced within the digital clock pulse signal. This could happen, for example, if the operator pulls out the wrong cable or switches off the wrong clock pulse generator by mistake.
Clock pulse signals are often distributed over paired cables as differential signals including a clock signal and an inverted clock signal. At the receiving end, a receiver will often transform the differential signal into a uni-polar signal. When such a clock cable is removed, one of the differential signals is often disconnected before the other. Thus, while a clock pulse signal is still being received, it will be degraded over many clock pulses, until the connection of the second of the differential signal pair is disconnected. In such a case, the differential receiver will continue to produce the degraded clock signal over many clock pulses. Further, even once both input terminals to the differential receiver are disconnected, the differential receiver will produce noise over many clock pulses, as such a differential receiver typically has considerable gain.
In a different situation, when the power to the clock pulse generator is switched off, often inadvertently, the signal level of the digital clock pulse signal will decay slowly, as compared to the clock period. At a certain point, the line receiver will no longer be able to detect the signal and will start to produce noise. In such circumstances, ordinary LOS detectors are slow to detect the loss of signal. Thus, a faulty signal can be transferred over a considerable number of clock pulses and will influence network synchronization in a negative way, typically resulting in data loss and/or network crashes.
It is an object of the invention to more quickly detect degradation and defects in a monitored or supervised digital clock pulse signal.
It is a further object of the present invention to detect the presence of spurious pulses or dropouts in the supervised digital clock pulse signal within a short time from the occurrence of such degradation.
It is an object to accomplish the above objects of the present invention with a monitoring circuit which operates asynchronously, and thus independently from the supervised or monitored digital clock pulse signal.
These objects are accomplished by a method and circuit which detects irregularity in the digital clock pulse train with a circuit which is driven by a reference pulse train developing a reference pulse train with pulses producing a monitoring period sufficient to ensure that the detected number of edges of the monitored pulse train, when exhibiting a normal clock rate, is within a desired range. While in the preferred embodiment, the minimum number of edges would typically be one, the concepts of the present application could be used in a detector which has a monitoring period that assures that more than one edge, for example, two edges, are sensed within the monitoring period for a monitored clock pulse train with a normal clock rate. Also, while a maximum number in the desired range is normally two, one leading and one trailing edge, another number may be selected. The reference pulse train employed by the system of the present application desirably has lands interposed between adjacent reference pulses, and which are longer than the longest of a single pulse or land of the monitored clock pulse train. The system of the present application desirably uses a reference clock pulse train that is generated asynchronously from the supervised or monitored clock pulse train.
The system of the present application detects logical low-to-high or logical high-to-low transitions (also known as leading and trailing edges) of the monitored clock pulse train and determines whether the number of leading and trailing edges of the monitored clock pulse train falls within a desired range. If the number of detected leading or trailing edges of the monitored clock pulse train which occur within a single reference pulse falls within a desired range, the monitored digital clock pulse train is determined to be regular. Otherwise, the monitored clock train is determined irregular.
According to the teachings of the present application, a reference clock pulse train is for example, configured with a fifty-percent duty cycle. Other duty cycles may be used. However, it is important for the pulses of the monitored pulse train to have a duration sufficient to ensure that the detected number of edges of the monitored clock pulse train when producing transitions at a normal clock pulse rate, is within a desired range, in one preferred embodiment at least one, but no more than two, one leading edges and one trailing edge. In the preferred embodiment, this pulse duration is preferably less than that of a full cycle of the monitor clock pulse train, but longer than both the pulse and land of a full-cycle.
The circuit and method of the present invention generally determines, during each monitoring period, the monitored or supervised clock pulse train to be regular if at least a specified range of clock edges, in the preferred embodiment, at least one leading or trailing edge but no more than one leading edge or one trailing edge are detected. Otherwise, the signal is determined irregular and an alarm is given.
In one preferred embodiment, the circuit employed in the system of the present application utilizes a pair of two-bit shift registers to store a count of the number of leading and trailing edges detected during a monitoring period. Logic is then utilized to determine whether the number of detected leading and trailing edges is representative of a regular or irregular signal. Of course, a shift register circuit such as that utilized in the preferred embodiment of the present invention requires a reset period. While the reset period may be shortened, transitions occurring within the reset period cannot be detected by a single pair of two-bit shift registers. Accordingly, in one embodiment of the present invention, the system seeks to shorten the reset period. However, even with a shortened reset period, such an embodiment has a blind period during which edges may not be detected, a circumstance which may be unacceptable in certain applications.
In a second embodiment of the present invention, two pairs of two-bit shift registers are utilized, one to monitor the clock pulse signal during the reset period of the other. Even in such an arrangement, if the reset signal supplied to these two two-bit shift registers are simply a phase inversion of one another, detection of leading or trailing edges during the transition between monitoring by these two detectors may not readily be performed. This can be corrected by shortening the reset period, creating overlap between the beginning of a new monitoring period and the end of an old monitoring period. Thus, in accordance with another embodiment, potential problems in this transition period are avoided through reconfiguration of the reference pulse train.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while illustrating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.